In march 2019 intel published a new white paper discussing a new bug they have found inside TSX and
the proposed fix. Even in whiskey lake, TSX is still somewhat broken.
The fix that intel has rolled out consists of two parts.
They have disabled the Hardware Lock Elision (HLM) variant of TSX and
they have rolled out a microcode patch for the
Restricted Transactional Memory (RTM) variant of TSX, that disables it
in SGX and SMM mode by aborting all transactions.
Bit 13 of the
EDX register of
0x07 indicates if the workaround is enabled.
To keep RTM working in non SMM and SGX mode, intel has sacrificed 1 of the 4 general purpose
performance counters (if hyper threading is disabled 1 of the 8).
When running RTM code counter number 3 is used by the
TSX microcode and can not be used by the user. To
still make it possible to use all performance counters there is a new
MSR register that will default abort TSX transactions,
if the MSR
0x10f) is set to 1,
all TSX transactions will abort on executing the commit instruction,
according to patch on lkml.
However after performing some tests,
it seems that the whole tsx block is ignored. Concluding that the
MSR will completly disable TSX with out trowing an undefined instruction